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[libcpu][risc-v] Fix PLIC interrupt processing order#11305

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Rbb666 merged 1 commit intoRT-Thread:masterfrom
FurryAcetylCoA:fix_plic
Apr 7, 2026
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[libcpu][risc-v] Fix PLIC interrupt processing order#11305
Rbb666 merged 1 commit intoRT-Thread:masterfrom
FurryAcetylCoA:fix_plic

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Description / 描述

This PR fixes the PLIC interrupt handling order in the RISC-V virt64 libcpu. The previous code called plic_complete before executing the interrupt handler, which violated the correct interrupt flow. According to Section 1.5 Interrupt Flow of the RISC-V Platform-Level Interrupt Controller Specification, the interrupt should be handled first and then completed.

本次 PR 修复了 RISC-V virt64 中的 PLIC 中断处理顺序。以往的代码在执行中断 handler 之前调用了 plic_complete。根据 RISC-V Platform-Level Interrupt Controller Specification 的 1.5. Interrupt Flow 节的说明,应当先运行 handler,然后再 complete。

Modified Files / 修改文件

  • libcpu/risc-v/virt64/plic.c: Fixed plic_handle_irq by moving plic_complete after the handler call.

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👋 感谢您对 RT-Thread 的贡献!Thank you for your contribution to RT-Thread!

为确保代码符合 RT-Thread 的编码规范,请在你的仓库中执行以下步骤运行代码格式化工作流(如果格式化CI运行失败)。
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@github-actions github-actions bot added Arch: RISC-V BSP related with risc-v libcpu labels Mar 31, 2026
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📌 Code Review Assignment

🏷️ Tag: libcpu_riscv

Reviewers: @Yaochenger

Changed Files (Click to expand)
  • libcpu/risc-v/virt64/plic.c

📊 Current Review Status (Last Updated: 2026-03-31 20:05 CST)


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@Rbb666 Rbb666 modified the milestones: v5.3.1, v5.2.2 Apr 7, 2026
@Rbb666 Rbb666 merged commit e3cfde2 into RT-Thread:master Apr 7, 2026
57 checks passed
@kurisaW kurisaW removed this from the v5.3.1 milestone Apr 7, 2026
@kurisaW kurisaW added the 5.3.0 label Apr 7, 2026
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4 participants